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| general description the DS28EA00 is a digital thermometer with 9-bit (0.5?)to 12-bit (1/16?) resolution and alarm function with non- volatile (nv), user-programmable upper and lower trigger points. each DS28EA00 has its own unique 64-bit regis- tration number that is factory programmed into the chip. data is transferred serially through the 1-wire protocol, which requires only one data line and a ground referencefor communication. the improved 1-wire front-end with hysteresis and glitch filter enables the DS28EA00 to per- form reliably in large 1-wire networks. unlike other 1-wire thermometers, the DS28EA00 has two additional pins to implement a sequence-detect function. this feature allows the user to discover the registration numbers according to the physical device location in a chain, e.g., to measure the temperature in a storage tower at different height. if the sequence-detect function is not needed, these pins can be used as general-purpose input or out- put. the DS28EA00 can derive the power for its operation directly from the data line (?arasite power?, eliminating the need for an external power supply. applications data communication equipmentprocess temperature monitoring hvac systems features ? digital thermometer measures temperaturesfrom -40? to +85? ? thermometer resolution is user selectable from9 to 12 bits ? unique 1-wire interface requires only one portpin for communication ? each device has a unique 64-bit, factory-lasered registration number ? multidrop capability simplifies distributedtemperature-sensing applications ? improved 1-wire interface with hysteresis andglitch filter ? user-definable nv alarm threshold settings/userbytes ? alarm search command to quickly identifydevices whose temperature is outside of programmed limits ? standard and overdrive 1-wire speed ? two general-purpose programmable io (pio) pins ? chain function sharing the pio pins to detectphysical sequence of devices in network ? operating range: +3.0v to +5.5v, -40? to +85? ? can be powered from data line ? 8-pin ?op package DS28EA00 1-wire digital thermometer with sequence detect and pio for pricing, delivery, and ordering information, please contact maxim directat 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. ordering information DS28EA00 io piob pioa gnd v dd v dd note: schematic shows pio pins wired for sequence-detect function. 1-wire master #1 DS28EA00 io piob px. y microcontroller pioa gnd v dd #2 DS28EA00 io piob pioa gnd v dd #3 typical operating circuit rev 2; 4/09 part temp range pin-package DS28EA00u+ -40 c to +85 c 8 sop DS28EA00u+t&r -40 c to +85 c 8 sop pin configuration appears at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. 1-wire is a registered trademark of maxim integrated products, inc. downloaded from: http:///
1-wire digital thermometer with sequence detect and pio DS28EA00 2 maxim integrated absolute maximum ratingselectrical characteristics (t a = -40? to +85?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. io voltage range to gnd ........................................-0.5v to +6v io sink current....................................................................20ma maximum pioa or piob pin current...................................20ma maximum current through gnd pin ..................................40ma operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-55? to +125? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units power supply supply voltage v dd (note 2) 3.0 5.5 v supply current (note 3) i dd v dd = +5.5v 1.5 ma standby current i dds v dd = +5.5v 1.5 a io pin: general data local power 3.0 v dd 1-wire pullup voltage (note 2) v pup parasite power 3.0 5.5 v 1-wire pullup resistance r pup (notes 2, 4) 0.3 2.2 k input capacitance c io (notes 3, 5) 1000 pf input load current i l io pin at v pup 0.1 1.5 a high-to-low switching threshold v tl (notes 3, 6, 7) 0.46 v pup - 1.9v v parasite powered 0.5 input low voltage (notes 2, 8) v il v dd powered (note 3) 0.7 v low-to-high switching threshold (notes 3, 6, 9) v th parasite power 1.0 v pup - 1.1v v switching hysteresis (notes 3, 6, 10) v hy parasite power 0.21 1.7 v output low voltage (note 11) v ol at 4ma 0.4 v standard speed, r pup = 2.2k 5 overdrive speed, r pup = 2.2k 2 recovery time (notes 2, 12) t rec overdrive speed, directly prior to reset pulse; r pup = 2.2k 5 s standard speed 0.5 5.0 rising-edge hold-off time (notes 3, 13) t reh overdrive speed not applicable (0) s standard speed 65 time-slot duration (notes 2, 14) t slot overdrive speed 8 s io pin: 1-wire reset, presence-detect cycle standard speed 480 640 reset low time (note 2) t rstl overdrive speed 48 80 s downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 3 electrical characteristics (continued)(t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units standard speed 15 60 presence-detect high time t pdh overdrive speed 2 6 s standard speed 1.125 8.1 presence-detect fall time (notes 3, 15) t fpd overdrive speed 0 1.3 s standard speed 60 240 presence-detect low time t pdl overdrive speed 8 24 s standard speed 68.1 75 presence-detect sample time (notes 2, 16) t msp overdrive speed 7.3 10 s io pin: 1-wire write standard speed 60 120 write-zero low time (notes 2, 17) t w0l overdrive speed 6 16 s standard speed 5 15 write-one low time (notes 2, 17) t w1l overdrive speed 1 2 s io pin: 1-wire read standard speed 5 15 - read low time (notes 2, 18) t rl overdrive speed 1 2 - s standard speed t rl + 15 read sample time (notes 2, 18) t msr overdrive speed t rl + 2 s pio pins input low voltage v ilp (note 2) 0.3 v input high voltage (note 2) v ihp v x = max(v pup , v dd ) v x - 1.6 v input load current (note 19) i lp pin at gnd -1.1 a output low voltage (note 11) v olp at 4ma 0.4 v chain-on pullup impedance r co (note 3) 20 40 60 k eeprom programming current i prog (notes 3, 20) 1.5 ma programming time t prog (note 21) 10 ms at +25c 200,000 write/erase cycles (endurance) (notes 22, 23) n cy -40c to +85c 50,000 data retention (notes 24, 25) t dr at +85c (worst case) 10 years temperature converter conversion current i conv (notes 3, 20) 1.5 ma 12-bit resolution (1/16c) 750 11-bit resolution (1/8c) 375 10-bit resolution (1/4c) 187.5 conversion time (note 26) t conv 9-bit resolution (1/2c) 93.75 ms -10c to +85c -0.5 +0.5 conversion error below -10c (note 3) -0.5 +2.0 c converter drift d (note 27) -0.2 +0.2 c downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 4 maxim integrated note 1: specifications at t a = -40? are guaranteed by design and not production tested. note 2: system requirement. note 3: guaranteed by design, characterization, and/or simulation only. not production tested. note 4: maximum allowable pullup resistance is a function of the number of 1-wire devices in the system and 1-wire recoverytimes. the specified value here applies to parasitically powered systems with only one device and with the minimum 1-wire recovery times. for more heavily loaded systems, local power or an active pullup such as that found in the ds2482-x00, ds2480b, or ds2490 may be required. if longer t rec is used, higher r pup values may be tolerable. note 5: value is 25pf maximum with local power. maximum value represents the internal parasite capacitance when v pup is first applied. if r pup = 2.2k , 2.5? after v pup has been applied, the parasite capacitance does not affect normal communications. note 6: v tl , v th , and v hy are a function of the internal supply voltage, which is a function v dd , v pup , r pup , 1-wire timing, and capacitive loading on io. lower v dd , v pup , higher r pup , shorter t rec , and heavier capacitive loading all lead to lower val- ues of v tl , v th , and v hy . note 7: voltage below which, during a falling edge on io, a logic 0 is detected. note 8: the voltage on io must be less than or equal to v ilmax at all times when the master drives the line to a logic 0. note 9: voltage above which, during a rising edge on io, a logic 1 is detected. note 10: after v th is crossed during a rising edge on io, the voltage on io must drop by at least v hy to be detected as logic 0. note 11: the i-v characteristic is linear for voltages less than +1v. note 12: applies to a single parasitically powered DS28EA00 attached to a 1-wire line. these values also apply to networks of multiple DS28EA00 with local supply . note 13: the earliest recognition of a negative edge is possible at t reh after v th has been reached on the preceding rising edge. note 14: defines maximum possible bit rate. equal to 1/(t w0lmin + t recmin ). note 15: interval during the negative edge on io at the beginning of a presence-detect pulse between the time at which the voltageis 80% of v pup and the time at which the voltage is 20% of v pup . note 16: interval after t rstl during which a bus master is guaranteed to sample a logic 0 on io if there is a DS28EA00 present. minimum limit is t pdhmax + t fpdmax ; the maximum limit is t pdhmin + t pdlmin . note 17: in figure 13 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - , respectively. note 18: in figure 13 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input-high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . note 19: this load current is caused by the internal weak pullup, which asserts a logic 1 to the piob and pioa pins. the logicalstate of piob must not change during the execution of the conditional read rom command. note 20: current drawn from io during eeprom programming or temperature conversion interval in parasite-powered mode. thepullup circuit on io during the programming or temperature conversion interval should be such that the voltage at io is greater than or equal to v pupmin . if v pup in the system is close to v pupmin , then a low-impedance bypass of r pup , which can be activated during programming or temperature conversions, may need to be added. the bypass must be activatedwithin 10? from the beginning of the t prog or t conv interval, respectively. note 21: the t prog interval begins t rehmax after the trailing rising edge on io for the last time slot of the command byte for a valid copy scratchpad sequence. interval ends once the device? self-timed eeprom programming cycle is complete and thecurrent drawn by the device has returned from i prog to i l (parasite power) or i dds (local power). note 22: write-cycle endurance is degraded as t a increases. note 23: not 100% production tested. guaranteed by reliability monitor sampling. note 24: data retention is degraded as t a increases. note 25: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to datasheet limit at operating temperature range is established by reliability testing. note 26: the t conv interval begins t rehmax after the trailing rising edge on io for the last time slot of the command byte for a valid convert temperature sequence. the interval ends once the device? self-timed temperature conversion cycle is completeand the current drawn by the device has returned from i conv to i l (parasite power) or i dds (local power). note 27: drift data is preliminary and based on a 1000-hour stress test performed on another device with comparable design andfabricated in the same manufacturing process. this test was performed at greater than +85? with v dd = +5.5v. confirmed thermal drift results for this device are pending the completion of a new 1000-hour stress test. electrical characteristics (continued)(t a = -40? to +85?.) (note 1) downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 5 pin description pin name function 1 io 1-wire bus interface and parasitic power supply. open-drain pin th at requires external pullup resistor. 2, 3, 5 n.c. no connection 4 gnd ground supply 6 pioa ( done ) open-drain pioa channel and chain output. for sequence detection, p ioa must be connected to piob of the next device in the chain; leave open or connect to gnd for the last device in the chain. 7 piob ( en ) open-drain piob channel and chain input. for sequence detection, p iob of the first device in the chain must be connected to gnd. 8 v dd power supply. must be connected to gnd for operation in parasite-power mo de. detailed description the block diagram shows the relationships between the major function blocks of the DS28EA00. the devicehas three main data components: 64-bit registration number, 64-bit scratchpad, and alarm and configura- tion registers. the 1-wire rom function control unit processes the rom function commands that allow the device to function in a networked environment. the device function control unit implements the device-spe- cific control functions, such as read/write, temperature conversion, setting the chain state for sequence detec- tion, and pio access. the cyclic redundancy check (crc) generator assists the master verifying data integrity when reading temperatures and memory data. in the sequence-detect process, piob functions as an input, while pioa provides the connection to the next device. the power-supply sensor allows the master to remotely read whether the DS28EA00 has local power available. figure 1 shows the hierarchical structure of the 1-wire protocol. the bus master must first provide one of the eight rom function commands: read rom, match rom, search rom, conditional (alarm) search rom, conditional read rom, skip rom, overdrive-skip rom, overdrive-match rom. upon completion of an overdrive rom command exe- cuted at standard speed, the device enters overdrive mode, where all subsequent communication occurs at a higher speed. the protocol required for these romfunction commands is described in figure 11. after a rom function command is successfully executed, the device-specific control functions become accessible and the master can provide any one of the nine avail- able commands. the protocol for these control function commands is described in figure 9. all data is read and written least significant (ls) bit first. 64-bit registration number each DS28EA00 contains a unique registration numberthat is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits (see figure 2 for details). the 1-wire crc is generated using a polyno- mial generator consisting of a shift register and xor gates as shown in figure 3. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the 1-wire crc is available in application note 27: understanding and using cyclic redundancy checks with maxim i button products . the shift register bits are initialized to 0. then startingwith the least significant bit of the family code, one bit at a time is shifted in. after the eighth bit of the family code has been entered, then the 48-bit serial number is entered. after the last byte of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of crc returns the shift register to all 0s. i button is a registered trademark of maxim integrated products, inc. downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 6 maxim integrated DS28EA00 power-supply sensor 64-bit scratchpad temperature sensor 8-bit crc generator 1-wire rom function control device function control alarm and configuration registers 64-bit registration number piob (en) pioa (done) io v dd (on) internal v dd r co block diagram available commands: data field affected: read rom match rom search rom conditional search rom conditional read rom skip rom overdrive-skip rom overdrive-match rom 64-bit rom64-bit rom 64-bit rom 64-bit rom, temperature alarm registers, scratchpad 64-bit rom, piob pin state, chain state (none) 64-bit rom, od-flag 64-bit rom, od-flag 1-wire rom function commands (see figure 11) write scratchpadread scratchpad copy scratchpad convert temperature read power mode recall eeprom pio access read pio access write chain scratchpadscratchpad temperature alarm and configuration registers scratchpad, temperature alarm registers v dd pin voltage scratchpad, temperature alarm, and configuration registerspio pins pio pins chain state, pioa pin state DS28EA00-specific control function commands (see figure 9) command level: DS28EA00 figure 1. hierarchical structure for 1-wire protocol downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 7 msb 8-bit crc code 48-bit serial number msb msb lsb lsblsb 8-bit family code (42h) msb lsb figure 2. 64-bit registration number 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 8 + x 5 + x 4 + 1 input data x 5 x 6 x 7 x 8 figure 3. 1-wire crc generator scratchpad (power-up state) byte address temperature lsb (50h) 0 temperature msb (05h) 1 th register or user byte 1* 2 tl register or user byte 2* *power-up state depends on value(s) stored in eeprom. 3 configuration register* 4 reserved (ffh) 5 reserved (0ch) 6 reserved (10h) backup eeprom n/a n/a th register or user byte 1 tl register or user byte 2 configuration register n/a n/a n/a 7 figure 4. memory map memory description the memory map of the DS28EA00 is shown in figure 4.it consists of an 8-byte scratchpad and 3 bytes of back- up eeprom. the first 2 bytes form the temperature readout register, which is updated after a temperature conversion and is read only. the next 3 bytes are user- writable; they contain the temperature high (th) and the temperature low (tl) alarm register and a configuration register. the remaining 3 bytes are ?eserved.?they power up with constant data and cannot be written bythe user. the th, tl, and configuration register data in the scratchpad control the resolution of a temperature conversion and decide whether a temperature is consid- ered as ?larming.?th, tl, and configuration can be copied to the eeprom to become nonvolatile. the scratchpad is automatically loaded with eeprom data when the DS28EA00 powers up. downloaded from: http:/// the temperature reading is in ? using a 16-bit sign-extended two? complement format. table 1 shows examples of temperature and the corresponding data for 12-bit resolution. with two? complement, the sign bit(s) is set if the value is negative. if the device is con- figured for 12-bit resolution, all bits in the ls byte are valid; for a reduced resolution, bit 0 (11-bit mode), bits 0 to 1 (10-bit mode), and bits 0 to 2 (9-bit mode) are undefined. the result of a temperature conversion is automatically compared to the values in the alarm registers to deter- mine whether an alarm condition exists. alarm thresh- olds are represented as two? complement number.with 8 bits available for sign and value, alarm thresh- olds can be set in increments of 1?. an alarm condi- tion exists if a temperature conversion results in a value that is either higher than or equal to the value stored in the th register or lower than or equal to the value stored in the tl register. if a temperature alarm condi-tion exists, the device responds to the conditional search rom command. the alarm condition is cleared if a subsequent temperature conversion results in a temperature reading within the boundaries defined by the data in the th and tl registers. 1-wire digital thermometer with sequence detect and pio DS28EA00 8 maxim integrated addrress bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0h 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 ls byte 1h s s s s s 2 6 2 5 2 4 ms byte temperature (c) digital output (binary) digital output (hex) +85* 0000 0101 0101 0000 0550h +25.0625 0000 0001 1001 0001 0191h +10.125 0000 0000 1010 0010 00a2h +0.5 0000 0000 0000 1000 0008h 0 0000 0000 0000 0000 0000h -0.5 1111 1111 1111 1000 fff8h -10.125 1111 1111 0101 1110 ff5eh -25.0625 1111 1110 0110 1111 fe6fh -40 1111 1101 1000 0000 fd80h table 1. temperature/data relationship * the power-on reset value of the temperature readout register is +85?. addrress bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 high alarm (th) 3h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 low alarm (tl) register detailed descriptions temperature readout register bitmap temperature alarm registers bitmap downloaded from: http:/// the functional assignments of the individual bits areexplained in the table below. bits [4:0] and bit 7 have no function and cannot be changed by the user. as afactory default, the device operates in 12-bit resolution. 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 9 addrress bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4h 0 r1 r0 1 1 1 1 1 bit description bit(s) definition r1, r0: temperature converter resolution [6:5] these bits control the resolution of the temperature converter. the codes are a s follows: r1 r0 0 0 9 bits 0 1 10 bits 1 0 11 bits 1 1 12 bits device behavior chain state piob ( en )p i o a ( done ) conditional read rom off (default) pio (high impedance) pio (high impedance) not recognized on en input pullup on recognized if en is 0 done no function pulldown on ( done logic 0) not recognized table 2. chain states pio structure each pio consists of an open-drain pulldown transistorand an input path to read the pin state. the transistor is controlled by the pio output latch, as shown in figure 5. the device function control unit connects the pio pins logically to the 1-wire interface. pioa has a pullup path to internal v dd to facilitate the sequence-detect function (see the block diagram ) in conjunction with the chain command; piob is truly an open-drain structure.the power-on default state of the pio output transistors is off; high-impedance, on-chip resistors (not shown in figure 5) pull the pio pins to internal v dd . chain function the chain function is a feature that allows the 1-wiremaster to discover the physical sequence of devices that are wired as a linear network (chain). this is partic- ularly convenient for devices that are installed at equal spacing along a long cable (e.g., to measure tempera- tures at different locations inside a storage tower or tank). without chain function, the master needs a lookup table to correlate the registration number to the physical location. the chain function requires two pins: an input ( en ) to enable a device to respond during the discovery andan output ( done ) to inform the next device in the chain that the discovery of its neighbor is done. the two gen- eral-purpose ports of the DS28EA00 are reused for thechain function. piob functions as an en input and pioa generates the done signal, which is connected to the en input of the next device, as shown in the typical operating circuit . the en input of the first device in the chain needs to be hardwired to gnd or logic 0 must beapplied for the duration of the sequence discovery process. besides the two pins, the sequence discovery relies on the conditional read rom command. for the chain function and normal pio operation to coexist, the DS28EA00 distinguishes three chain states: off, on, and done. the transition from one chain state to another is controlled through the chain com- mand. table 2 summarizes the chain states and the specific behavior of the pio pins. d qq pio output latch clock pio pin pio pin state pio output latch state pio data pio clock figure 5. pio simplified logic diagram configuration register downloaded from: http:/// the power-on default chain state is off, where pioaand piob are solely controlled through the pio access read and write commands. in the chain on state, pioa is pulled high to the device? internal v dd supply through an approximately 40k resistor, applying a logic 1 to the piob ( en ) pin of the next device. only in the on state does a DS28EA00 respond to theconditional read rom command, provided its en is at logic 0. after a device? rom registration number isread, it is put into the chain done state, which enables the next device in the chain to respond to the conditional read rom command. at the beginning of the sequence discovery process, all devices are put into the chain on state. as the discov- ery progresses, one device after another is transitioned into the done state until all devices are identified. finally, all devices are put into the chain off state, which releases the pio pins and restores their power- on default state. control function commands figure 9 shows the protocols necessary for measuringtemperatures, accessing the memory and pio pins, and changing the chain state. examples on how to use these and other functions are included at the end of this document. the communication between master and DS28EA00 takes place either at standard speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into the overdrive mode after power-up, the DS28EA00 communicates at standard speed. write scratchpad [4eh] this command allows the master to write 3 bytes ofdata to the scratchpad of the DS28EA00. the first data byte is associated with the th register (byte address 2), the second byte is associated with the tl register (byte address 3), and the third byte is associated with the configuration register (byte address 4). data must be transmitted least significant bit first. all 3 bytes must be written before the master issues a reset, or the data can be corrupted. read scratchpad [beh] this command allows the master to read the contentsof the scratchpad. the data transfer starts with the least significant bit of the temperature readout register at byte address 0 and continues through the remaining 7 bytes of the scratchpad. if the master continues read- ing, it gets a ninth byte, which is an 8-bit crc of all the data in the scratchpad. this crc is generated by the DS28EA00 and uses the same polynomial function as is used with the rom registration number. the crc istransmitted in its true (noninverted) form. the master can issue a reset to terminate the reading early if only part of the scratchpad data is needed. copy scratchpad [48h] this command copies the contents of the scratchpadbyte addresses 2 to 4 (th, tl, and configuration regis- ters) to the backup eeprom. if the device has no v dd power, the master must enable a strong pullup on the1-wire bus for the duration of t progmax within 10? after this command is issued. if the device is poweredthrough the v dd pin, the master can generate read time slots to monitor the copy process. copy is completedwhen the master reads 1 bits instead of 0 bits. convert temperature [44h] this command initiates a temperature conversion.following the conversion, the resulting thermal data is found in the temperature readout register in the scratchpad and the DS28EA00 returns to its low-power idle state. if the device has no v dd power, the master must enable a strong pullup on the 1-wire bus for theduration of the applicable resolution-dependent t convmax within 10? after this command is issued. if the device is powered through the v dd pin, the master can generate read time slots to monitor the conversionprocess. the conversion is completed when the master reads 1 bits instead of 0 bits. read power mode [b4h] for copy scratchpad and convert temperature, themaster needs to know whether the DS28EA00 has v dd power available. the read power mode command isimplemented to provide the master with this informa- tion. after the command code, master issues read time slots. if the master reads 1s, the device is powered through the v dd pin. if the device is powered through the 1-wire line, the master read 0s. the power-supplysensor samples the state of the v dd pin for every time slot that the master generates after the command code. recall eeprom [b8h] this command recalls the th and tl alarm trigger val-ues and configuration data from backup eeprom into their respective locations in the scratchpad. after hav- ing transmitted the command code, the master can issue read time slots to monitor the completion of the recall process. recall is completed when the master reads 1 bits instead of 0 bits. the recall occurs auto- matically at power-up, not requiring any activity by the master. 1-wire digital thermometer with sequence detect and pio DS28EA00 10 maxim integrated downloaded from: http:/// pio access read [f5h] this command reads the pio logical status and reportsit together with the state of the pio output latch in an endless loop. a pio access read can be terminated at any time with a 1-wire reset. pio access read can be executed in the chain on and chain done state. while the device is in the chain on or chain done state, the pio output latch states always read out as 1s; the pio pin state may not be reported correctly. the state of both pio channels is sampled at the same time. the first sampling occurs during the last (most significant) bit of the command code f5h. the pio sta- tus is then reported to the bus master. while the master receives the last (most significant) bit of the pio status byte, the next sampling occurs and so on until the mas- ter generates a 1-wire reset. the sampling occurs with a delay of t reh + x from the rising edge of the ms bit of the previous byte, as shown in figure 6. the value of??is approximately 0.2?. pio access write [a5h] the pio access write command writes to the pio out-put latches, which control the pulldown transistors of the pio channels. in an endless loop, this command first writes new data to the pio and then reads back the pio status. this implicit read-after-write can be used by the master for status verification. a pio access write can be terminated at any time with a 1-wire reset. the pio access write command is ignored by the device while in chain on or chain done state. after the command code, the master transmits a pio output data byte that determines the new state of the pio output transistors. the first (least significant) bit is associated to pioa; the next bit affects piob. the other 6 bits of the new state byte do not have corresponding pio pins. these bits should always be transmitted as 1s. to switch the output transistor on, the corresponding bit value is 0. to switch the output transistor off (non-con- ducting), the bit must be 1. this way the bit transmitted 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 11 pio status bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 complement of b3 to b0 piob output latch state piob pin state pioa output latch state pioa pin state pio output data bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x x piob pioa sampling point** t reh + x v th io*the "previous byte" could be the command code or the data byte resulting from the previous pio sample. **the sample point timing also applies to the pio access write command, with the "previous byte" being the write confirmation byte (aah). most significant 2 bits of previous byte* least significant 2 bits of pio status byte figure 6. pio access read timing diagram downloaded from: http:/// as the new pio output state arrives in its true form at thepio pin. to protect the transmission against data errors, the master must repeat the pio output data byte in its inverted form. only if the transmission was error-free can the pio status change. the actual pio transition to the new state occurs with a delay of t reh + x from the rising edge of the ms bit of the inverted pio byte, as shown infigure 7. the value of ??is approximately 0.2?. to inform the master about the successful communication of the pio byte, the DS28EA00 transmits a confirmation byte with the data pattern aah. while the ms bit of the confirmation byte is transmitted, the DS28EA00 samples the state of the pio pins, as shown in figure 6, and sends it to the master. the master can either continue writing more data to the pio or issue a 1-wire reset to end the command. chain [99h] this command allows the master to put the DS28EA00into one of the three chain states, as shown in figure 8. the device powers up in the chain off state. to transi- tion a DS28EA00 from one state to another, the master must send a suitable chain control byte after the chain command code. only the codes 3ch, 5ah, and 96h (true form) are valid, assigned to off, on, and done, in this sequence. this control byte is first transmitted inits true form and then in its inverted form. if the chain state change was successful, the master receives aah confirmation bytes. if the change was not successful (control byte transmission error, invalid control byte), the master reads 00h bytes instead. 1-wire digital thermometer with sequence detect and pio DS28EA00 12 maxim integrated t reh + x v th io pio most significant 2 bits of inverted pio output data byte least significant 2 bits of confirmation byte (aah) figure 7. pio access write timing diagram these transitions are permissible, but do notoccur during normal operation. off power-on reset (por) chain done chain on chain on chain done chain off or por done on figure 8. chain state transition diagram downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 13 bus master tx control function command DS28EA00 sets byte address = 2 4eh write scratchpad? ny yn n y n master tx reset? byte address = 4? master tx reset? master tx data byte to scratchpad DS28EA00 increments byte address from rom functions flowchart (figure 11) to rom functions flowchart (figure 11) y to figure 9b from figure 9b DS28EA00 sets byte address = 0 DS28EA00 starts copy to eeprom beh read scratchpad? n y master rx byte from scratchpad master activates strong pullup for t prog master deactivates strong pullup DS28EA00 copies scratchpad data to eeprom 48h copy scratchpad? master decision.the master needs to know whether v dd power is available. n y y n y v dd powered? copy completed? master rx "0"s master rx "1"s y nn master tx reset? byte address = 7? DS28EA00 increments byte address master rx 8-bit crc of data n y n master tx reset? y master rx "1"s n master tx reset? y figure 9a. control function flowchart downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 14 maxim integrated to figure 9c from figure 9c from figure 9ato figure 9a DS28EA00 starts temperature conversion master activates strong pullup for t conv master deactivates strong pullup DS28EA00 converts temperature 44h convert temperature n y y b4h read power mode? n y n n y n y v dd powered? v dd powered? conversion completed? master rx "0"s master rx "1"s master rx "0"s master rx "1"s n master tx reset? y n master tx reset? y master decision. the master needs to know whether v dd power is available. figure 9b. control function flowchart downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 15 to figure 9d from figure 9d from figure 9bto figure 9b DS28EA00 starts recall eeprom to scratchpad DS28EA00 samples pio pin * *see the command description for the exact timing of the pio pin sampling and updating. DS28EA00 updates pio * * bus master tx new pio output data byte bus master tx inverted new pio output data byte bus master rx pio pin status b8h recall eeprom? n y f5h pio access read? a5h pio access write? n n y recall completed? y n n master rx "0"s master rx "1"s master rx "1"s n master tx reset? y n n y master tx reset? n master tx reset? y transmission ok? master tx reset? bus master rx confirmation aah bus master rx "1"s bus master rx pio pin status DS28EA00 samples pio pin y y y figure 9c. control function flowchart downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 16 maxim integrated from figure 9cto figure 9c 99h chain command? n y master rx "1"s n master tx reset? y n master tx chain control byte DS28EA00 updates chain state master rx confirmation code aah master tx inverted chain control byte transmission error? control byte valid? y n n y master tx reset? y n master rx inverted chain control byte master tx reset? y n master rx error code 00h master tx reset? y error defined as:repeated control byte not equal to inverted control byte valid chain control byte codes: 3ch off5ah on 96h done figure 9d. control function flowchart downloaded from: http:/// 1-wire bus system the 1-wire bus is a system that has a single bus masterand one or more slaves. in all instances the DS28EA00 is a slave device. the bus master is typically a micro- controller. the discussion of this bus system is broken down into three topics: hardware configuration, trans- action sequence, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transac- tions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1-wire bus has only a single line by definition; it isimportant that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open-drain or three-state outputs. the 1-wire port of the DS28EA00 is open drain with an internal circuit equivalent to that shown in figure 10. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the DS28EA00 supports both a stan- dard and overdrive communication speed of 15.3kbps (max) and 125kbps (max), respectively. note that lega- cy 1-wire products support a standard communication speed of 16.3kbps and overdrive of 142kbps. the slightly reduced rates for the DS28EA00 are a result of additional recovery times, which in turn are driven by a 1-wire physical interface enhancement to improvenoise immunity. the value of the pullup resistor primari- ly depends on the network size and load conditions. the DS28EA00 requires a pullup resistor of 2.2k (max) at any speed.the idle state for the 1-wire bus is high. if for any rea- son a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16? (overdrive speed) or more than 120? (standard speed), one or more devices on the bus could be reset. transaction sequence the protocol for accessing the DS28EA00 through the1-wire port is as follows: ? initialization ? rom function command ? control function command ? transaction/data initialization all transactions on the 1-wire bus begin with an initial-ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the DS28EA00 is on the bus and is ready to operate. for more details, see the 1-wire signaling section. 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 17 rx r pup i l v pup bus master open-drain port pin 100 mosfet tx rxtx data DS28EA00 1-wire port rx = receive tx = transmit figure 10. hardware configuration downloaded from: http:/// 1-wire rom function commands once the bus master has detected a presence, it canissue one of the eight rom function commands that the DS28EA00 supports. all rom function commands are 8 bits long. a list of these commands follows (refer to the flowchart in figure 11). read rom [33h] this command allows the bus master to read theDS28EA00? 8-bit family code, unique 48-bit serial num- ber, and 8-bit crc. this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-and result). the resultant fami- ly code and 48-bit serial number result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit romsequence, allows the bus master to address a specific DS28EA00 on a multidrop bus. only the DS28EA00 that exactly matches the 64-bit rom sequence responds to the following control function command. all other slaves wait for a reset pulse. this command can be used with a single device or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus mastermight not know the number of devices on the 1-wire bus or their registration numbers. by taking advantage of the wired-and property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. for each bit of the regis- tration number, starting with the least significant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search outputs the true value of its registration number bit. on the sec- ond slot, each slave device participating in the search outputs the complemented value of its registration num- ber bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participat- ing in the search. if both of the read bits are zero, the master knows that slave devices exist with both statesof the bit. by choosing which state to write, the bus master branches in the rom code tree. after one com- plete pass, the bus master knows the registration num- ber of a single device. additional passes identify the registration numbers of the remaining devices. refer to application note 187: 1-wire search algorithm for a detailed discussion, including an example. the searchrom command does not reveal any information about the location of a device in a network. if multiple DS28EA00 are wired as a linear network (?hain?, the device location can be detected using conditional read rom in conjunction with the chain function. conditional search rom [ech] the conditional search rom command operates similar-ly to the search rom command except that only those devices which fulfill certain conditions, participate in the search. this function provides an efficient means for the bus master to identify devices on a multidrop system that have to signal an important event. after each pass of the conditional search that successfully determined the 64-bit rom code for a specific device on the multidrop bus, that particular device can be individually accessed as if a match rom had been issued, since all other devices have dropped out of the search process and are waiting for a reset pulse. the DS28EA00 responds to the conditional search rom command if a temperature alarm condition exists. for more details see the temperature alarm registers bitmap section. conditional read rom [0fh] this command is used in conjunction with the chainfunction to detect the physical sequence of devices in a linear network (chain). a DS28EA00 responds to conditional read rom if two conditions are met: a) the device is in chain on state, and b) the en input (piob) is at logic 0. this condition is met by exactly one deviceduring the sequence discovery process. upon receiv- ing the conditional read rom command, this particu- lar device transmits its 64-bit registration number. a device in chain on state, but with a logic 1 level at en does not respond to conditional read rom. see the sequence discovery procedure section for more details on the use of conditional read rom and the chaincommands. 1-wire digital thermometer with sequence detect and pio DS28EA00 18 maxim integrated downloaded from: http:/// skip rom [cch] this command can save time in a single-drop bus sys-tem by allowing the bus master to access the control functions without providing the 64-bit rom code. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-and result). overdrive-skip rom [3ch] on a single-drop bus this command can save time byallowing the bus master to access the control functions without providing the 64-bit rom code. unlike the nor- mal skip rom command, the overdrive-skip rom sets the DS28EA00 in the overdrive mode (od = 1). all com- munication following this command has to occur at overdrive speed until a reset pulse of minimum 480? duration resets all devices on the bus to standard speed (od = 0). when issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. to subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom com-mand sequence. this speeds up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive-skip rom command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired- and result). overdrive-match rom [69h] the overdrive-match rom command followed by a64-bit rom sequence transmitted at overdrive speed allows the bus master to address a specific DS28EA00 on a multidrop bus and to simultaneously set it in over- drive mode. only the DS28EA00 that exactly matches the 64-bit rom sequence responds to the subsequent control function command. slaves already in overdrive mode from a previous overdrive-skip rom or success- ful overdrive-match rom command remain in over- drive mode. all overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480? duration. the overdrive-match rom command can be used with a single device or multiple devices on the bus. 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 19 downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 20 maxim integrated DS28EA00 tx presence pulse bus master tx reset pulse bus master tx rom function command DS28EA00 tx crc byte DS28EA00 tx family code (1 byte) DS28EA00 tx serial number (6 bytes) od = 0 master tx bit 0 y od reset pulse? y yy y y y n 33h read rom command? n 55h match rom command? bit 0 match? bit 0 match? n n n n n n n f0h search rom command? n ech conditional search command? n y master tx bit 1 master tx bit 63 bit 1 match? bit 63 match? y y from control functions flowchart (figure 9) to control functions flowchart (figure 9) DS28EA00 tx bit 0 DS28EA00 tx bit 0 master tx bit 0 bit 1 match? bit 63 match? DS28EA00 tx bit 1 DS28EA00 tx bit 1 master tx bit 1 DS28EA00 tx bit 63 DS28EA00 tx bit 63 master tx bit 63 y bit 0 match? n n n y y DS28EA00 tx bit 0 DS28EA00 tx bit 0 master tx bit 0 temperature alarm? n y bit 1 match? bit 63 match? DS28EA00 tx bit 1 DS28EA00 tx bit 1 master tx bit 1 DS28EA00 tx bit 63 DS28EA00 tx bit 63 master tx bit 63 y from figure 11b to figure 11bto figure 11b from figure 11b figure 11a. rom functions flowchart downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 21 master tx bit 0 od = 1 od = 1 od = 0 * *the od flag remains at 1 if the device was already at overdrive speed before the overdrive-match rom command was issued. ** chain = on? y n y cch skip rom command? n y 3ch overdrive- skip rom? n y en = low? y y 0fh conditional read rom? y 69h overdrive- match rom? n n nn od = 0 n od = 0 n master tx bit 1 master tx bit 63 y y y bit 0 match? master tx reset? bit 63 match? bit 1 match? n y master tx reset? n to figure 11afrom figure 11a from figure 11a to figure 11a DS28EA00 tx family code (1 byte) DS28EA00 tx serial number (6 bytes) DS28EA00 tx crc byte figure 11b. rom functions flowchart downloaded from: http:/// 1-wire signaling the DS28EA00 requires strict protocols to ensure dataintegrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and pres- ence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all falling edges. the DS28EA00 can communicate at two different speeds, standard speed and overdrive speed. if not explicitly set into the overdrive mode, the DS28EA00 communicates at standard speed. while in overdrive mode the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 12 as ?and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1-wire network attached.the voltage v ilmax is relevant for the DS28EA00 when determining a logical level, not triggering any events.figure 12 shows the initialization sequence required to begin any communication with the DS28EA00. a reset pulse followed by a presence pulse indicates the DS28EA00 is ready to receive data, given the correct rom and control function command. if the bus master uses slew-rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480? or longer exits the overdrive mode, returning the device to standard speed. if theDS28EA00 is in overdrive mode and t rstl is no longer than 80?, the device remains in overdrive mode. if the device is in overdrive mode and t rstl is between 80? and 480?, the device resets, but the communicationspeed is undetermined. after the bus master has released the line, it goes into receive mode. now the 1-wire bus is pulled to v pup through the pullup resistor, or in the case of a ds2482-x00 or ds2480b driver, by active circuitry. when the threshold v th is crossed, the DS28EA00 waits for t pdh and then transmits a presence pulse by pulling the linelow for t pdl . to detect a presence pulse, the master must test the logical state of the 1-wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the DS28EA00 is ready for data communica-tion. in a mixed population network, t rsth should be extended to minimum 480? at standard speed and48? at overdrive speed to accommodate other 1-wire devices. read/write time slots data communication with the DS28EA00 takes place intime slots, which carry a single bit each. write time slots transport data from bus master to slave. read time slots transfer data from slave to master. figure 13 illus- trates the definitions of the write and read time slots. all communication begins with the master pulling the data line low. as the voltage on the 1-wire line falls below the threshold v tl , the DS28EA00 starts its inter- nal timing generator that determines when the data lineis sampled during a write time slot and how long data is valid during a read time slot. 1-wire digital thermometer with sequence detect and pio DS28EA00 22 maxim integrated resistor master DS28EA00 t rstl t pdl t rsth t pdh master tx "reset pulse" master rx "presence pulse" v pup v ihmaster v th v tl v ilmax 0v t f t rec t msp figure 12. initialization procedure ?eset and presence pulses downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 23 resistor master resistor master resistor master DS28EA00 v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l t rec t slot t slot t w0l t rec master sampling window t rl t msr write-one time slotwrite-zero time slot read-data time slot figure 13. read/write timing diagram downloaded from: http:/// 1-wire digital thermometer with sequence detect and pio DS28EA00 24 maxim integrated master-to-slave for a write-one time slot, the voltage on the data line must have crossed the v th threshold before the write- one low time t w1lmax is expired. for a write-zero time slot, the voltage on the data line must stay below thev th threshold until the write-zero low time t w0lmin is expired. for the most reliable communication, the volt-age on the data line should not exceed v ilmax during the entire t w0l or t w1l window. after the v th threshold has been crossed, the DS28EA00 needs a recoverytime t rec before it is ready for the next time slot. slave-to-master a read-data time slot begins like a write-one time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl window, when responding with a 0, the DS28EA00starts pulling the data line low; its internal timing gener- ator determines when this pulldown ends and the volt- age starts rising again. when responding with a 1, the DS28EA00 does not hold the data line low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise time) on one side and the inter- nal timing generator of the DS28EA00 on the other sidedefine the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the mastershould read close to but no later than t msrmax . after reading from the data line, the master must wait untilt slot is expired. this guarantees sufficient recovery time t rec for the DS28EA00 to get ready for the next time slot. note that t rec specified herein applies only to a single DS28EA00 attached to a 1-wire line. for multideviceconfigurations, t rec needs to be extended to accommo- date the additional 1-wire device input capacitance.alternatively, an interface that performs active pullup dur- ing the 1-wire recovery time such as the ds2482-x00 or ds2480b 1-wire line drivers can be used. improved network behavior (switchpoint hysteresis) in a 1-wire environment, line termination is possibleonly during transients controlled by the bus master (1-wire driver). 1-wire networks, therefore, are suscep- tible to noise of various origins. depending on the phys- ical size and topology of the network, reflections from end points and branch points can add up, or cancel each other to some extent. such reflections are visible as glitches or ringing on the 1-wire communication line. noise coupled onto the 1-wire line from external sources can also result in signal glitching. a glitch dur- ing the rising edge of a time slot can cause a slave device to lose synchronization with the master and,consequently, result in a search rom command com- ing to a dead end or cause a device-specific function command to abort. for better performance in network applications, the DS28EA00 uses a new 1-wire front- end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself. the 1-wire front-end of the DS28EA00 differs from tra- ditional slave devices in four characteristics: 1) the falling edge of the presence pulse has a con- trolled slew rate. this provides a better match to theline impedance than a digitally switched transistor, converting the high-frequency ringing known from traditional devices into a smoother low-bandwidth transition. the slew-rate control is specified by the parameter t fpd , which has different values for stan- dard and overdrive speed. 2) there is additional lowpass filtering in the circuit that detects the falling edge at the beginning of atime slot. this reduces the sensitivity to high-fre- quency noise. this additional filtering does not apply at overdrive speed. 3) there is a hysteresis at the low-to-high switching threshold v th . if a negative glitch crosses v th but does not go below v th - v hy , it is not recognized (figure 14, case a). the hysteresis is effective atany 1-wire speed. 4) there is a time window specified by the rising edge hold-off time t reh during which glitches are ignored, even if they extend below v th - v hy threshold (figure 14, case b, t gl < t reh ). deep voltage droops or glitches that appear late aftercrossing the v th threshold and extend beyond the t reh window cannot be filtered out and are taken as the beginning of a new time slot (figure 14, case c,t gl t reh ). devices that have the parameters v hy and t reh speci- fied in their electrical characteristics use the improved1-wire front-end. sequence discovery procedure precondition: the piob pin ( en ) of the first device in the chain is at logic 0. the pioa pin ( done ) of the first device connects to the piob of the second device inthe chain, etc., as shown in figure 15. the 1-wire mas- ter detects the physical sequence of the devices in the chain by performing the following procedure. starting condition: the master issues a skip rom command followed by a chain on command, whichputs all devices in the chain on state. the pullup downloaded from: http:/// through r co of the pioa pin charges the pioa/piob connections to logic 1 level at all devices except for thefirst device in the chain. if a local v dd supply is not available, the master needs to activate a low-imped-ance bypass to the 1-wire pullup resistor immediately after the inverted chain control byte until the pioa/piob connections have reached a voltage equivalent to the logic 1 level. first cycle: the master sends a conditional read rom command, which causes the first device in the chain torespond with its 64-bit registration number. the master memorizes the registration number and the fact that this is the first device in the chain. next, the master transmits a chain done command. through the pioa pin of the just discovered device, this asserts logic 0 at the piob pin of the second device in the chain and also prevents the just discovered device from responding again. second cycle: the master sends a conditional read rom command. since the second DS28EA00 is the only device in the chain with a low level at piob, itresponds with its registration number. the master stores the registration number with the sequence num- ber of 2. the first device cannot respond since it is in chain done state. next, the master transmits a chain done command. additional cycles: to identify the registration numbers of the remaining devices and their physical sequence,the master repeats the steps of conditional read rom and chain done. if there is no response to conditional read rom, all devices in the chain are identified. ending condition: at the end of the discovery process all devices in the chain are in the chain done state.the master should end the sequence discovery by issuing a skip rom command followed by a chain off command. this puts all the devices into the chain off state and transfers control of the piob and pioa pins to the pio access read and write function commands. 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 25 v pup v th v hy 0v t reh t gl t reh t gl case a case c case b figure 14. noise suppression scheme DS28EA00 io piob pioa gnd v dd v dd *capacitance of the cabling between adjacent devices in the chain. ** 1-wire master #1 DS28EA00 io piob px. y microcontroller pioa gnd v dd #2 DS28EA00 io piob pioa gnd v dd #3 figure 15. DS28EA00 wired for sequence discovery (?hain function? downloaded from: http:/// command-specific 1-wire communication protocol?egend 1-wire digital thermometer with sequence detect and pio DS28EA00 26 maxim integrated symbol description rst 1-wire reset pulse generated by master pd 1-wire presence pulse generated by slave select command and data to satisfy the rom function protocol skipr rom function command: skip rom cdrr rom function command: conditional read rom wsp command: write scratchpad rsp command: read scratchpad cpsp command: copy scratchpad ctemp command: convert temperature rpm command: read power mode rcle command: recall eeprom pior command: pio access read piow command: pio access write chain command : chain 1-wire communication examples 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim integrated 27 rst wsp write scratchpad pd rst pd select <3 bytes> <8 bytes> ff loop rst rsp rpm crc read scratchpad pd select rst convert temperature (parasite powered) pd select ff loop rst convert temperature (local v dd powered) pd select ff loop during the wait, the master should activate a low-impedancebypass to the 1-wire pullup resistor. during the wait, the master should activate a low-impedancebypass to the 1-wire pullup resistor. see the command description for behavior if the device is in chainon or chain done state. rst copy scratchpad (parasite powered) pd cps select wait t progmax ff loop wait t convmax ff loop the master reads 00h bytes until the write cycle is completed. rst copy scratchpad (local v dd powered) pd cps <00h> <00h> <00h> rpm 1-wire digital thermometer with sequence detect and pio DS28EA00 28 maxim integrated 1-wire communication examples (continued) rst pio access write (invalid data byte) pd select ff loop aa loop 00 loop xx loop rst change chain state (success) pd select chain chain chain chain chain rst change chain state (transmission error) pd select the pio access write command is ignored by the device while in chain on or chain done state. rst change chain state (invalid control byte) pd select rst pd <5ah> 1-wire digital thermometer with sequence detect and pio DS28EA00 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 29 2009 maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/07 initial release. 1 6/07 changed the storage temperature range in the absolute maimum ratings section from -40c to +85c to -55c to +125c. 2 2 4/09 created newer template-style data s heet. all downloaded from: http:/// |
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